Burn-in method and burn-in device

ABSTRACT

To provide a burn-in method and device capable of accelerating burn-in also in a peripheral circuit portion and a logic circuit portion as well as a memory cell array portion. A high temperature stress is applied to a wafer to be an evaluation object (Step SP 11 ). Next, a low temperature stress and an electric stress are applied to the wafer (Step SP 12 ). Then, it is decided whether a predetermined stress is applied to the wafer or not (Step SP 13 ). If a result of the decision at the Step SP 13  is “YES”, it is decided whether a defective portion is generated in each chip of the wafer or not (Step SP 14 ). Referring to a chip decided to have a failure generated thereon as a result of the decision at the Step SP 14,  it is decided whether repair is executed for the defective portion or not (Step SP 15 ). If a result of the decision at the Step SP 15  is “YES”, the repair is executed for the defective portion (Step SP 16 ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a burn-in method and device forcarrying out a reliability test of a semiconductor device, and moreparticularly to a wafer level burn-in method and device for carrying outa test in a state of a wafer.

[0003] 2. Description of the Background Art

[0004] A burn-in test of the semiconductor device is an accelerationtest for applying, to the semiconductor device, a higher voltage stressor a higher temperature stress than that in the case in which thesemiconductor device is actually used as a product and for evaluating anelectrical characteristic of the semiconductor device after theapplication of the stress, thereby screening the semiconductor devicegenerating initial failures or the semiconductor device having thecharacteristic keeping away from a normal distribution.

[0005] Conventionally, a wafer test has been carried out, anon-defective chip passing the wafer test has been assembled and theburn-in test of the semiconductor device has been executed in a packagecondition in which the assembly is sealed with a package (a package suchas a resin, ceramic or plastics). More specifically, a large number ofpackaged semiconductor devices are provided on a burn-in board and aburn-in stress is collectively applied in a thermostat. Thus, theelectrical characteristic of each semiconductor device is evaluatedafter the application of the stress.

[0006]FIG. 19 is a flow chart for explaining a conventional burn-inmethod. First of all, a high temperature stress and an electric stressare applied to a wafer to be an evaluation object (Step SP101). Morespecifically, the electric stress is applied in a state in which thewafer is put in a high temperature furnace or the electric stress isexternally applied in a state in which the wafer is mounted on a hightemperature chuck.

[0007] Next, it is decided whether a predetermined stress is applied tothe wafer or not (Step SP102). At the Step SP102, if it is decided thatthe predetermined stress is not applied to the wafer, the processingreturns to the Step SP101 where the high temperature stress and theelectric stress are applied again.

[0008] On the other hand, if it is decided that the predetermined stressis applied to the wafer at the Step SP102, it is decided whether adefective portion is generated in each chip of the wafer or not(PASS/FAIL decision) (Step SP103). Furthermore, if a failure isgenerated, the defective portion is identified.

[0009] As a result of the PASS/FAIL decision at the Step SP103, it isdecided whether a defective portion is to be repaired or not for a chipwhich is decided to have a failure generated thereon (Step SP104). If aresult of the decision at the Step SP104 is “YES”, the defective portionis repaired (Step SP105).

[0010] A chip decided as “PASS” at the Step SP103 and a chip repaired atthe Step SP105 are subjected to an assembling step and a packaging stepand are then shipped as products. On the other hand, a chip decided as“NO” at the Step SP104 (that is, a chip which generates a failure andcannot be repaired) is not subjected to the assembling step and the likeand is treated as a defective chip.

[0011]FIG. 20 is a top view typically showing a structure of asemiconductor memory to be an evaluation object of burn-in. A chip 101has a plurality of memory cell array portions 102, a peripheral circuitportion 103 and a logic circuit portion 104. Each memory cell arrayportion 102 is provided with a plurality of memory cells arranged in amatrix, a plurality of word lines for each row of the memory cell arrayand a plurality of bit lines for each column of the memory cell array. Aperipheral circuit such as a sense amplifier is formed in the peripheralcircuit portion 103 together with a plurality of wirings. A random logiccircuit is formed in the logic circuit portion 104 together with aplurality of wirings.

[0012] As a method of efficiently carrying out the burn-in by using thesemiconductor memory as an object, there have been proposed a method ofselecting all bit lines and all word lines at the same time andcollectively applying an electrical stress to all memory cells (JapanesePatent Application Laid-Open No. 5-144910 (1993)) and a method ofselecting all bit lines and half of word lines at the same time andcollectively applying an electrical stress to memory cells (half of allthe memory cells) connected to the word lines (Japanese PatentApplication Laid-Open No. 4-756 (1992)). In such a method, a selectivityof the word line in the memory cell array portion 102 is more enhancedthan that in an actual usage state. As compared with the case in whichthe word lines are selected one by one to carry out the burn-in as inthe actual usage state, a time required for the burn-in can beshortened. In other words, the burn-in can be accelerated.

[0013] Referring to the wiring of the peripheral circuit portion 103 andthe wiring of the logic circuit portion 104, however, there is a portionwhere all the wirings cannot be collectively selected electrically inrespect of a structure. In the conventional burn-in method, therefore,there has been a problem in that it is hard to accelerate the burn-in inthe peripheral circuit portion 103 and the logic circuit portion 104. Inthe conventional burn-in method in which only a high temperature stressand an electric stress are applied, particularly, a large number of testpatterns of the electric stress are required for applying the electricstress to whole wirings of the logic circuit portion 104. Therefore,there has been a problem in that the burn-in cannot be accelerated infact.

SUMMARY OF THE INVENTION

[0014] A first aspect of the present invention is directed to a burn-inmethod comprising the steps of (a) applying one of a high temperaturestress and a low temperature stress to an evaluation object, (b)applying an electric stress and the other of the high temperature stressand the low temperature stress to the evaluation object, and (c)deciding whether a failure is generated on the evaluation object or notafter the steps (a) and (b).

[0015] A second aspect of the present invention is directed to theburn-in method according to the first aspect, wherein the steps (a) and(b) are executed repetitively.

[0016] A third aspect of the present invention is directed to a burn-indevice comprising one of a high temperature generating portion and a lowtemperature generating portion which has mounting surface where anevaluation object is to be mounted, the other of the high temperaturegenerating portion and the low temperature generating portion which isprovided opposite to the mounting surface of the one of the hightemperature generating portion and the low temperature generatingportion and can be moved relatively to the one of the high temperaturegenerating portion and the low temperature generating portion, anelectric stress applying portion for applying an electric stress to theevaluation object, and an evaluating portion for deciding whether afailure is generated on the evaluation object or not.

[0017] A fourth aspect of the present invention is directed to theburn-in device according to the third aspect, wherein the other of thehigh temperature generating portion and the low temperature generatingportion is provided with a plurality of through holes penetrating fromone main surface opposed to the mounting surface to the other mainsurface.

[0018] A fifth aspect of the present invention is directed to theburn-in device according to the third aspect, wherein the other of thehigh temperature generating portion and the low temperature generatingportion partially applies a temperature stress to the evaluation object.

[0019] A sixth aspect of the present invention is directed to theburn-in device according to any one of the third to fifth aspects,further comprising a driving mechanism for driving at least one of thehigh temperature generating portion and the low temperature generatingportion, and a control portion for controlling the driving mechanism.

[0020] A seventh aspect of the present invention is directed to theburn-in device according to the sixth aspect, further comprising atemperature sensor connected to the control portion and provided closeto the evaluation object.

[0021] An eighth aspect of the present invention is directed to theburn-in device according to the sixth or seventh aspect, wherein theelectric stress applying portion is connected to the control portion.

[0022] According to the first aspect of the present invention, the hightemperature stress and the low temperature stress are appliedconsecutively. Consequently, the generation of failures caused by athermal stress can be accelerated efficiently.

[0023] According to the second aspect of the present invention, the hightemperature stress and the low temperature stress are appliedrepetitively. Consequently, a great burn-in stress can be applied to theevaluation object.

[0024] According to the third aspect of the present invention, the hightemperature stress and the low temperature stress are applied from thehigh temperature generating portion and the low temperature generatingportion to the evaluation object, respectively. Consequently, thegeneration of failures caused by the thermal stress can be acceleratedefficiently.

[0025] According to the fourth aspect of the present invention, the gasis blown against the other main surface of the other of the hightemperature generating portion and the low temperature generatingportion. Consequently, a gas having a high temperature or a lowtemperature which is heated or cooled when passing through a throughhole can be blown against the evaluation object.

[0026] According to the fifth aspect of the present invention, the hightemperature portion obtained by the application of the high temperaturestress from the high temperature generating portion and the lowtemperature portion obtained by the application of the low temperaturestress from the low temperature generating portion can be fabricated inthe evaluation object. Consequently, the generation of failures can beaccelerated by utilizing a bias of a stress caused by a temperaturegradient in the evaluation object or the like.

[0027] According to the sixth aspect of the present invention, themoving speed and stop position of at least one of the high temperaturegenerating portion and the low temperature generating portion can becontrolled by the control portion and the driving mechanism. Therefore,it is possible to accurately control the temperature stress to beapplied to the evaluation object.

[0028] According to the seventh aspect of the present invention, thecontrol portion can control each temperature of the high temperaturegenerating portion and the low temperature generating portion based ontemperature data transferred from the temperature sensor. Therefore, thetemperature stress to be applied to the evaluation object can becontrolled to have a desirable value.

[0029] According to the eighth aspect of the present invention, all theapplication of the high temperature stress through the high temperaturegenerating portion, the application of the low temperature stressthrough the low temperature generating portion and the application ofthe electric stress through the electric stress applying portion arecontrolled by the control portion. Therefore, it is possible to enhancecontrollability as a system of a whole burn-in device.

[0030] In order to solve the above-mentioned problems, it is an objectof the present invention to provide a burn-in method and a burn-indevice which can accelerate burn-in in a peripheral circuit portion anda logic circuit portion as well as a memory cell array portion.

[0031] These and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a flow chart for explaining a burn-in method accordingto a first embodiment of the present invention;

[0033]FIGS. 2 and 3 are side views typically showing a part of astructure of a burn-in device according to a second embodiment of thepresent invention,

[0034]FIG. 4 is a sectional view typically showing a part of a structureof a burn-in device according to a third embodiment of the presentinvention,

[0035]FIG. 5 is a side view typically showing a part of a structure of aburn-in device according to a fourth embodiment of the presentinvention,

[0036]FIG. 6 is a block diagram typically showing a part of a structureof a burn-in device according to a fifth embodiment of the presentinvention,

[0037]FIG. 7 is a block diagram typically showing a part of a structureof a burn-in device according to a sixth embodiment of the presentinvention,

[0038] FIGS. 8 to 10 are block diagrams typically showing a part of astructure of a burn-in device according to a seventh embodiment of thepresent invention,

[0039]FIG. 11 is a flow chart for explaining a burn-in method accordingto an eighth embodiment of the present invention,

[0040]FIGS. 12 and 13 are side views typically showing a part of astructure of a burn-in device according to a ninth embodiment of thepresent invention,

[0041]FIG. 14 is a sectional view typically showing a part of astructure of a burn-in device according to a tenth embodiment of thepresent invention,

[0042]FIG. 15 is a side view typically showing a part of a structure ofa burn-in device according to an eleventh embodiment of the presentinvention,

[0043]FIG. 16 is a block diagram typically showing a part of a structureof a burn-in device according to a twelfth embodiment of the presentinvention,

[0044]FIG. 17 is a block diagram typically showing a part of a structureof a burn-in device according to a thirteenth embodiment of the presentinvention,

[0045]FIG. 18 is a block diagram typically showing a part of a structureof a burn-in device according to a fourteenth embodiment of the presentinvention,

[0046]FIG. 19 is a flow chart for explaining a conventional burn-inmethod, and

[0047]FIG. 20 is a top view typically showing a structure of asemiconductor memory to be an evaluation object of burn-in.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] First Embodiment

[0049]FIG. 1 is a flow chart for explaining a burn-in method accordingto a first embodiment of the present invention. First of all, apredetermined high temperature stress is applied to a wafer to be anevaluation object (Step SP11). For example, the wafer is put in a hightemperature furnace set to have a predetermined temperature for apredetermined time or the wafer is mounted on a high temperature chuckset to have a predetermined temperature for a predetermined time.

[0050] Next, a predetermined low temperature stress and a predeterminedelectric stress are applied to the wafer having the high temperaturestress applied thereto (Step SP12). For example, the electric stress isapplied in a state in which the wafer is put in a low temperaturefurnace set to have a predetermined temperature or the electric stressis applied in a state in which the wafer is mounted on a low temperaturechuck set to have a predetermined temperature. The application of theelectric stress is carried out by using a well-known probe card having aplurality of probe needles.

[0051] Next, it is decided whether a predetermined stress is applied tothe wafer or not (Step SP13). For example, a step of a test is preset toa burn-in device and it is decided whether the application of thepredetermined stress is completed or not depending on whether the numberof applications of the stress or a time required for the applicationreaches a set value or not. At the Step SP13, if it is decided that thenumber of applications of the stress or the time required for theapplication does not reach the set value, the processing returns to theSteps SP11 and SP12 where the temperature stress and the electric stressare applied again.

[0052] On the other hand, if it is decided that the predetermined stressis applied at the Step SP 13, it is decided whether a defective portionis generated in each chip of the wafer or not (PASS/FAIL decision) (StepSP14). The PASS/FAIL decision is executed in an evaluating portionprovided in the burn-in device. More specifically, a current isexternally applied to a circuit fabricated in the chip and a value ofthe current flowing in the circuit is measured to decide the generationof failures. Furthermore, if a failure is generated, the defectiveportion is identified. Alternatively, address data are externally inputto the circuit and the generation of failures is decided based on aresult of an output. Furthermore, if a failure is generated, thedefective portion is identified.

[0053] Referring to a chip decided to have the failure generated thereonas a result of the PASS/FAIL decision at the Step SP14, it is decidedwhether the defective portion is to be repaired or not (Step SP15). The“repair” implies that a circuit having failures generated due to adisconnection or the like is replaced with another equivalent circuitwhich is prepared in advance. In the case in which a failure isgenerated on a portion in which a circuit for replacement is notprepared or the case in which circuits for replacement are prepared buta large number of chips generate the same defective portions so that thecircuits for replacement are used up, the same portion cannot berepaired and it is decided that the repair is not executed.

[0054] Whether the repair can be carried out is decided as follows. Dataindicative of a relationship between a defective portion and the numberof circuits for replacement are previously taught to a burn-in device.The device automatically decides repairable/disable in relation to eachdefective portion by referring to the data. Based on information aboutthe defective portion, an operator may decide the repairable/disable. Ifa result of the decision at the Step SPl5 is “YES”, the defectiveportion is repaired (Step SP16).

[0055] A chip decided as “PASS” at the Step SP14 and a chip repaired atthe Step SP16 are subjected to an assembling step and a packaging stepand are shipped as products. On the other hand, a chip decided as “NO”at the Step SP15 (that is, a chip which has a failure generated thereonand cannot be repaired) is not subjected to the assembling step and thelike and is treated as a defective chip.

[0056] According to the burn-in method in accordance with the firstembodiment, thus, a high temperature stress is applied and a lowtemperature stress and an electric stress are then applied to carry outthe burn-in differently from the conventional burn-in method of applyingonly the high temperature stress and the electric stress. Bycontinuously applying the high temperature stress and the lowtemperature stress, the generation of failures caused by a thermalstress can be accelerated efficiently. In addition, the thermal stressis increased when the low temperature stress is applied. Therefore, whenthe electric stress is further applied in a low temperature state inwhich a great internal stress is generated, the generation of failurescaused by the internal stress can further be accelerated. As a result, ascreening efficiency can be enhanced.

[0057] Moreover, a high temperature stress and a low temperature stresswhich are used as a burn-in stress are also applied uniformly to aregion in a chip which is hard to uniformly apply the electric stress(for example, a peripheral circuit portion and a logic circuit portion).Consequently, uniformity of the applied stress can be enhanced. Thus,the burn-in having a high reliability can be carried out for a widerange as an object at a time.

[0058] Furthermore, a defective portion which can be repaired issubjected to the repair and is then subjected to assembly and packaging.Thus, a non-defective device can be shipped. Consequently, it ispossible to increase the number of chips per wafer which are obtained asnon-defective devices, resulting in an enhancement in yield.

[0059] Second Embodiment

[0060] In a second embodiment, there will be proposed a burn-in devicecapable of efficiently executing application of a temperature cyclestress in relation to the burn-in method according to the firstembodiment.

[0061]FIGS. 2 and 3 are side views typically showing a part of astructure of the burn-in device according to the second embodiment ofthe present invention. A wafer 1 to be an evaluation object is mountedon a wafer mounting surface of a low temperature generating portion (forexample, a disc-shaped low temperature chuck 2L) for generating apredetermined low temperature. The low temperature chuck 2L cools thewafer 1 down to a predetermined temperature through liquid nitrogenintroduced to the inside or a Peltier element provided on the inside.Moreover, a high temperature generating portion (for example, adisc-shaped high temperature member 3H) for generating a predeterminedhigh temperature is opposed close to the low temperature chuck 2L. Thehigh temperature member 3H serves to generate a predetermined hightemperature by means of a heater provided on the inside. In place of thehigh temperature member 3H, a heating lamp may be provided. When atleast one of the low temperature chuck 2L and the high temperaturemember 3H is driven in a vertical or transverse direction, they arerelatively movable.

[0062] When the high temperature stress is to be applied to the wafer 1at the Step SP11 in the burn-in method according to the firstembodiment, the low temperature chuck 2L and the high temperature member3H are caused to approach to each other as shown in FIG. 2.Consequently, the application of the low temperature stress from the lowtemperature chuck 2L is offset and the high temperature stress isapplied to the wafer 1 by radiation heat sent from the high temperaturemember 3H.

[0063] When the low temperature stress and the electric stress are to beapplied to the wafer 1 at the Step SP12 in the burn-in method accordingto the first embodiment, the low temperature chuck 2L and the hightemperature member 3H are caused to keep away from each other, therebyapplying the low temperature stress to the wafer 1 through the lowtemperature chuck 2L. As shown in FIG. 3, furthermore, a plurality ofprobe needles 5 of a probe card 4 are caused to abut on the wafer 1,thereby applying the electric stress from the probe card 4 to the wafer1.

[0064] If the result of the decision at the Step SP13 in the burn-inmethod according to the first embodiment is “NO”, it is preferable thatthe above-mentioned operation should be executed repetitively in orderto repetitively apply the high temperature stress and the lowtemperature stress to the wafer 1.

[0065] According to the burn-in device in accordance with the secondembodiment, thus, the wafer 1 is mounted on the low temperature chuck2L, and the low temperature chuck 2L and the high temperature member 3Hare caused to approach to each other or to keep away from each other.Thus, control is carried out to apply the high temperature stress or thelow temperature stress to the wafer 1. Accordingly, when the lowtemperature stress is to be applied after the high temperature stress isapplied to the wafer 1, it is not necessary to mount the wafer 1 on thelow temperature chuck in place of the high temperature chuck or it isnot necessary to deliver the wafer 1 from a high temperature furnace toa low temperature furnace. Therefore, a time required for the burn-incan be shortened.

[0066] Third Embodiment

[0067]FIG. 4 is a sectional view typically showing a part of a structureof a burn-in device according to a third embodiment of the presentinvention. A high temperature member 3H according to the thirdembodiment is constituted by the high temperature member 3H according tothe second embodiment shown in FIG. 2 and is provided with a pluralityof through holes 7. The through holes 7 are discretely formed topenetrate from a top surface of the high temperature member 3H to abottom surface thereof (a main surface on the side opposite to a wafer1).

[0068] When a high temperature stress is to be applied to the wafer 1 atthe Step SP11 in the burn-in method according to the first embodiment, alow temperature chuck 2L and the high temperature member 3H are causedto approach to each other and a gas 8 such as nitrogen or dry air isblown against a top surface of the high temperature member 3H as shownin FIG. 4. The gas 8 is heated by the high temperature member 3H whenpassing through the through hole 7 and is thereby changed into a hightemperature gas 8H to be blown against the wafer 1.

[0069] According to the burn-in device in accordance with the thirdembodiment, thus, a high temperature stress can be applied to the wafer1 through radiation heat sent from the high temperature member 3H andthe blowing of the high temperature gas 8H. By regulating a flow rate ofthe gas 8, accordingly, the high temperature stress to be applied to thewafer 1 can be controlled.

[0070] Fourth Embodiment

[0071]FIG. 5 is a side view typically showing a part of a structure of aburn-in device according to a fourth embodiment of the presentinvention. In place of the disc-shaped high temperature member 3H shownin FIG. 2, a triangle pole-shaped high temperature member 9H having asharp side opposed to a low temperature chuck 2L is provided. The hightemperature member 9H serves to generate a predetermined hightemperature by means of a heater provided on the inside in the samemanner as the high temperature member 3H. When at least one of the hightemperature member 9H and the low temperature chuck 2L is driven in avertical or transverse direction, they are relatively movable.

[0072] When a high temperature stress is to be applied to a wafer 1 atthe step SP11 in the burn-in method according to the first embodiment,the high temperature member 9H is swept in the transverse direction withthe low temperature chuck 2L and the high temperature member 9Happroaching to each other as shown in FIG. 5.

[0073] According to the burn-in device in accordance with the fourthembodiment, thus, the whole surface of the wafer 1 is not uniformly setto have a high temperature through the disc-shaped high temperaturemember 3H but a part of the wafer 1 is locally set to have a hightemperature through the triangle pole-shaped high temperature member 9H.Accordingly, a high temperature portion obtained by application of ahigh temperature stress from the high temperature member 9H and a lowtemperature portion obtained by application of a low temperature stressfrom the low temperature chuck 2L can be fabricated in a wafer surface.Consequently, generation of failures can be accelerated by utilizing abias of a stress and a movement phenomenon of an aluminum atom in awiring or the like which are caused by a temperature gradient in thewafer surface. Thus, screening can be carried out efficiently.

[0074] Fifth Embodiment

[0075]FIG. 6 is a block diagram typically showing a part of a structureof a burn-in device according to a fifth embodiment of the presentinvention. A burn-in device 10 comprises a low temperature chuck 2L anda high temperature member 3H in the same manner as that in the secondembodiment. In the fifth embodiment, the low temperature chuck 2L isfixed. Moreover, the burn-in device 10 comprises a driving mechanism 12for driving the high temperature member 3H in a vertical direction (anda transverse direction if necessary) and a controller 11 connected tothe driving mechanism 12.

[0076] When a high temperature stress is to be applied to a wafer 1 atthe Step SP11 in the burn-in method according to the first embodiment,the driving mechanism 12 drives the high temperature member 3H downwardbased on a control signal S2 sent from the controller 11. The controlsignal S2 serves to control a moving speed of the high temperaturemember 3H and a stop position of the high temperature member 3H.Consequently, the low temperature chuck 2L and the high temperaturemember 3H approach to each other as shown in FIG. 6 so that a hightemperature stress is applied to the wafer 1.

[0077] Moreover, when the Step SP12 in the burn-in method according tothe first embodiment is to be executed, the driving mechanism 12 drivesthe high temperature member 3H upward based on the control signal S2sent from the controller 11. Consequently, the low temperature chuck 2Land the high temperature member 3H keep away from each other so that alow temperature stress is applied to the wafer 1. In addition, anelectric stress is externally applied to the wafer 1.

[0078] As shown in FIG. 6, a temperature sensor 13 may further beprovided on the low temperature chuck 2L close to the wafer 1, and thetemperature sensor 13, the low temperature chuck 2L and the hightemperature member 3H may be connected to the controller 11. Thecontroller 11 receives temperature data D1 from the temperature sensor13 and inputs control signals S1 and S2 to the low temperature chuck 2Land the high temperature member 3H, respectively. Consequently,temperatures of the low temperature chuck 2L and the high temperaturemember 3H are controlled, respectively.

[0079] While the description has been given to the example in which theburn-in device 10 according to the fifth embodiment is constituted basedon the burn-in device according to the second embodiment, the burn-indevice 10 according to the fifth embodiment can also be constitutedbased on the burn-in devices according to the third and fourthembodiments.

[0080] According to the burn-in device 10 in accordance with the fifthembodiment, thus, the moving speed and stop position of the hightemperature member 3H are controlled by the controller 11 and thedriving mechanism 12. Therefore, the high temperature stress to beapplied to the wafer 1 by the high temperature member 3H can becontrolled accurately.

[0081] Moreover, each temperature of the low-temperature chuck 2L andthe high temperature member 3H is controlled by the controller 11 basedon the temperature data D1 transmitted from the temperature sensor 13.Therefore, the low temperature stress and the high temperature stresswhich are to be applied to the wafer 1 can be controlled to havedesirable values.

[0082] Sixth Embodiment

[0083]FIG. 7 is a block diagram typically showing a part of a structureof a burn-in device according to a sixth embodiment of the presentinvention. A burn-in device 14 further comprises an electric stressapplying portion to be controlled by a controller 11 based on theburn-in device 10 according to the fifth embodiment. The electric stressapplying portion includes a probe card 4 having a plurality of probeneedles 5 and a driving mechanism 15 for driving the probe card 4 invertical and transverse directions. The driving mechanism 15 isconnected to the controller 1 1.

[0084] When the Step SP12 in the burn-in method according to the firstembodiment is to be executed, the driving mechanism 12 drives a hightemperature member 3H upward based on a control signal S2 sent from thecontroller 11 so that a low temperature stress is applied to a wafer 1through a low temperature chuck 2L. In addition, the driving mechanism15 drives the probe card 4 such that the probe needle 5 abuts on thewafer 1 based on a control signal S4 sent from the controller 11.Consequently, an electric stress is applied to the wafer 1 by the probecard 4. The control signal S4 serves to control a stop position of theprobe card 4 and to give the probe card 4 an instruction for applyingthe electric stress and a test pattern obtained at that time. Thecontrol signal S4 is input to the probe card 4 through the drivingmechanism 15.

[0085] According to the burn-in device 14 in accordance with the sixthembodiment, thus, the driving operation of the electric stress applyingportion for applying the electric stress to the wafer 1 is alsocontrolled by the controller 11. Therefore, it is possible to enhancecontrollability as a system of the whole burn-in device.

[0086] Seventh Embodiment

[0087] FIGS. 8 to 10 are block diagrams typically showing a part of astructure of a burn-in device according to a seventh embodiment of thepresent invention. For simplicity of the drawings, the temperaturesensor 13 shown in FIG. 6 is omitted. A burn-in device 16 comprises alow temperature chuck 2L and a high temperature member 3H in the samemanner as that in the second embodiment. In the seventh embodiment, thehigh temperature member 3H is fixed. Moreover, the burn-in device 16comprises a driving mechanism 17 for driving the low temperature chuck2L in vertical and transverse directions. Furthermore, the burn-indevice 16 comprises an electric stress applying portion having a probecard 4 fixed thereto. The driving mechanism 17 and the probe card 4 areconnected to a controller 11. In the same manner as in the fifthembodiment, the temperature sensor 13 (not shown), the low temperaturechuck 2L and the high temperature member 3H are connected to thecontroller 11.

[0088] Referring to FIG. 9, when a high temperature stress is to beapplied to a wafer 1 at the Step SP11 in the burn-in method according tothe first embodiment, the driving mechanism 17 drives the lowtemperature chuck 2L to approach to the high temperature member 3H basedon a control signal S2 sent from the controller 11. The control signalS2 serves to control a moving speed of the low temperature chuck 2L anda stop position of the low temperature chuck 2L. Consequently, the lowtemperature chuck 2L and the high temperature member 3H approach to eachother so that the high temperature stress is applied to the wafer 1.

[0089] Referring to FIG. 10, when a low temperature stress and anelectric stress are to be applied to the wafer 1 at the Step SP12 in theburn-in method according to the first embodiment, the driving mechanism17 drives the low temperature chuck 2L such that the wafer 1 abuts on aprobe needle 5 based on the control signal S2 sent from the controller11. Consequently, the low temperature stress is applied to the wafer 1by the low temperature chuck 2L and the electric stress is applied tothe wafer 1 by the probe card 4 based on a control signal S4 sent fromthe controller 11. The control signal S4 serves to give the probe card 4an instruction for applying the electric stress and a test patternobtained at that time.

[0090] While the description has been given to the example in which theburn-in device 16 according to the seventh embodiment is constitutedbased on the burn-in device according to the second embodiment, theburn-in device 16 according to the seventh embodiment can also beconstituted based on the burn-in devices according to the third andfourth embodiments.

[0091] According to the burn-in device 16 in accordance with the seventhembodiment, thus, the application of the high temperature stress throughthe high temperature member 3H, the application of the low temperaturestress through the low temperature chuck 2L and the application of theelectric stress through the probe card 4 are controlled by thecontroller 11. Therefore, it is possible to enhance controllability as asystem of the whole burn-in device.

[0092] Eighth Embodiment

[0093]FIG. 11 is a flow chart for explaining a burn-in method accordingto an eighth embodiment of the present invention. First of all, apredetermined low temperature stress is applied to a wafer to be anevaluation object (Step SP21). For example, the wafer is put in a lowtemperature furnace set to have a predetermined temperature for apredetermined time or the wafer is mounted on a low temperature chuckset to have a predetermined temperature for a predetermined time.

[0094] Next, a predetermined high temperature stress and a predeterminedelectric stress are applied to the wafer having the low temperaturestress applied thereto (Step SP22). For example, the electric stress isapplied in a state in which the wafer is put in a high temperaturefurnace set to have a predetermined temperature or the electric stressis applied in a state in which the wafer is mounted on a hightemperature chuck set to have a predetermined temperature.

[0095] Next, it is decided whether a predetermined stress is applied tothe wafer or not (Step SP23). If a result of the decision is “NO” at theStep SP23, the processing returns to the Steps SP21 and SP22 where theapplication of the temperature stress and the electric stress isexecuted again. On the other hand, if the result of the decision is“YES” at the Step SP23, a PASS/FAIL decision is carried out (Step SP24).Subsequently, it is decided whether repair is to be executed or not(Step SP25) and the repair is properly executed (Step SP26) in the samemanner as in the first embodiment.

[0096] According to the burn-in method in accordance with the eighthembodiment, thus, a low temperature stress is applied and a hightemperature stress and an electric stress are then applied to carry outthe burn-in differently from the conventional burn-in method of applyingonly the high temperature stress and the electric stress. Bycontinuously applying the low temperature stress and the hightemperature stress, the generation of failures caused by a thermalstress can be accelerated efficiently. In addition, the generation offailures of the device is accelerated more easily when the hightemperature stress is applied. Therefore, when the electric stress isfurther applied in a high temperature state, the generation of failurescaused by the thermal stress can further be accelerated. As a result, ascreening efficiency can be enhanced.

[0097] In the same manner as the burn-in method according to the firstembodiment, moreover, the uniformity of the burn-in stress can beenhanced through the application of the temperature stress. In addition,the execution of repair can also contribute to an enhancement in yield.

[0098] Ninth Embodiment

[0099] In a ninth embodiment, there will be proposed a burn-in devicecapable of efficiently executing application of a temperature cyclestress in relation to the burn-in method according to the eighthembodiment.

[0100]FIGS. 12 and 13 are side views typically showing a part of astructure of the burn-in device according to the ninth embodiment of thepresent invention. A wafer 1 is mounted on a wafer mounting surface of ahigh temperature generating portion (for example, a disc-shaped hightemperature chuck 2H). The high temperature chuck 2H serves to heat thewafer 1 to a predetermined temperature by means of a heater provided onthe inside. Moreover, a low temperature generating portion (for example,a disc-shaped low temperature member 3L) is opposed close to the hightemperature chuck 2H. The low temperature member 3L serves to generate apredetermined low temperature through liquid nitrogen introduced to theinside or a Peltier element provided on the inside. When at least one ofthe high temperature chuck 2H and the low temperature member 3L isdriven in a vertical or transverse direction, they are relativelymovable.

[0101] When the low temperature stress is to be applied to the wafer 1at the Step SP21 in the burn-in method according to the eighthembodiment, the high temperature chuck 2H and the low temperature member3L are caused to approach to each other as shown in FIG. 12.Consequently, the application of the high temperature stress from thehigh temperature chuck 2H is offset so that the low temperature stressis applied to the wafer 1.

[0102] When the high temperature stress and the electric stress are tobe applied to the wafer 1 at the Step SP22 in the burn-in methodaccording to the eighth embodiment, the high temperature chuck 2H andthe low temperature member 3L are caused to keep away from each other,thereby applying the high temperature stress to the wafer 1 through thehigh temperature chuck 2H. As shown in FIG. 13, furthermore, a pluralityof probe needles 5 of a probe card 4 are caused to abut on the wafer 1,thereby applying the electric stress from the probe card 4 to the wafer1.

[0103] According to the burn-in device in accordance with the ninthembodiment, thus, the wafer 1 is mounted on the high temperature chuck2H, and the high temperature chuck 2H and the low temperature member 3Lare caused to approach to each other or to keep away from each other.Consequently, control is carried out to apply the low temperature stressor the high temperature stress to the wafer 1. Accordingly, when thehigh temperature stress is to be applied after the low temperaturestress is applied to the wafer 1, it is not necessary to mount the wafer1 on the high temperature chuck in place of the low temperature chuck orit is not necessary to deliver the wafer 1 from a low temperaturefurnace to a high temperature furnace. Therefore, a time required forthe burn-in can be shortened.

[0104] Tenth Embodiment

[0105]FIG. 14 is a sectional view typically showing a part of astructure of a burn-in device according to a tenth embodiment of thepresent invention. A low temperature member 3L according to the tenthembodiment is constituted by the low temperature member 3L according tothe ninth embodiment shown in FIG. 12 and is discretely provided with aplurality of through holes 7.

[0106] When a low temperature stress is to be applied to a wafer 1 atthe Step SP2 1 in the burn-in method according to the eighth embodiment,a high temperature chuck 2H and the low temperature member 3L are causedto approach to each other and a gas 8 such as nitrogen or dry air isblown against a top surface of the low temperature member 3L as shown inFIG. 14. The gas 8 is cooled by the low temperature member 3L whenpassing through the through hole 7 and is thereby changed into a lowtemperature gas 8L to be blown against the wafer 1.

[0107] According to the burn-in device in accordance with the tenthembodiment, thus, a low temperature stress can be applied to the wafer 1by the low temperature member 3L and the low temperature gas 8L. Byregulating a flow rate of the gas 8, accordingly, the low temperaturestress to be applied to the wafer 1 can be controlled.

[0108] Eleventh Embodiment

[0109]FIG. 15 is a side view typically showing a part of a structure ofa burn-in device according to an eleventh embodiment of the presentinvention. In place of the disc-shaped shaped low temperature member 3Lshown in FIG. 12, a triangle pole-shaped low temperature member 9Lhaving a sharp side opposed to a high temperature chuck 2H is provided.The low temperature member 9L serves to generate a predetermined lowtemperature through liquid nitrogen introduced to the inside or aPeltier element provided on the inside in the same manner as the lowtemperature member 3L. When at least one of the low temperature member9L and the high temperature chuck 2H is driven in a vertical ortransverse direction, they are relatively movable.

[0110] When a low temperature stress is to be applied to a wafer 1 atthe Step SP21 in the burn-in method according to the eighth embodiment,the low temperature member 9L is swept in the transverse direction withthe high temperature chuck 2H and the low temperature member 9Lapproaching to each other as shown in FIG. 15.

[0111] According to the burn-in device in accordance with the eleventhembodiment, thus, the whole surface of the wafer 1 is not uniformly setto have a low temperature through the disc-shaped low temperature member3L but a part of the wafer 1 is locally set to have a low temperaturethrough the triangle pole-shaped low temperature member 9L. Accordingly,a low temperature portion obtained by application of a low temperaturestress from the low temperature member 9L and a high temperature portionobtained by application of a high temperature stress from the hightemperature chuck 2H can be fabricated in a wafer surface. Consequently,generation of failures can be accelerated by utilizing a bias of astress and a movement phenomenon of an aluminum atom in a wiring or thelike which are caused by a temperature gradient in the wafer surface.Thus, screening can be carried out efficiently.

[0112] Twelfth Embodiment

[0113]FIG. 16 is a block diagram typically showing a part of a structureof a burn-in device according to a twelfth embodiment of the presentinvention. A burn-in device 20 comprises a high temperature chuck 2H anda low temperature member 3L in the same manner as that in the ninthembodiment. In the twelfth embodiment, the high temperature chuck 2H isfixed. Moreover, the burn-in device 20 comprises a driving mechanism 12for driving the low temperature member 3L in a vertical direction (and atransverse direction if necessary) and a controller 11 connected to thedriving mechanism 12.

[0114] When a low temperature stress is to be applied to a wafer 1 atthe Step SP21 in the burn-in method according to the eighth embodiment,the driving mechanism 12 drives the low temperature member 3L downwardbased on a control signal S2 sent from the controller 11. Consequently,the high temperature chuck 2H and the low temperature member 3L approachto each other as shown in FIG. 16 so that a low temperature stress isapplied to the wafer 1.

[0115] Moreover, when the Step SP22 in the burn-in method according tothe eighth embodiment is to be executed, the driving mechanism 12 drivesthe low temperature member 3L upward based on the control signal S2 sentfrom the controller 11. Consequently, the high temperature chuck 2H andthe low temperature member 3L keep away from each other so that a hightemperature stress is applied to the wafer 1. In addition, an electricstress is externally applied to the wafer 1.

[0116] While the description has been given to the example in which theburn-in device 20 according to the twelfth embodiment is constitutedbased on the burn-in device according to the ninth embodiment, theburn-in device 20 according to the twelfth embodiment can also beconstituted based on the burn-in devices according to the tenth andeleventh embodiments.

[0117] According to the burn-in device 20 in accordance with the twelfthembodiment, thus, the moving speed and stop position of the lowtemperature member 3L are controlled by the controller 11 and thedriving mechanism 12. Therefore, the low temperature stress to beapplied to the wafer 1 by the low temperature member 3L can becontrolled accurately.

[0118] Thirteenth Embodiment

[0119]FIG. 17 is a block diagram typically showing a part of a structureof a burn-in device according to a thirteenth embodiment of the presentinvention. A burn-in device 21 further comprises an electric stressapplying portion to be controlled by a controller 11 based on theburn-in device 20 according to the twelfth embodiment. In the samemanner as in the sixth embodiment, the electric stress applying portionincludes a probe card 4 and a driving mechanism 15. The drivingmechanism 15 is connected to the controller 11.

[0120] When the Step SP22 in the burn-in method according to the eighthembodiment is to be executed, the driving mechanism 12 drives a lowtemperature member 3L upward based on a control signal S2 sent from thecontroller 11 so that a high temperature stress is applied to a wafer 1through a high temperature chuck 2H. In addition, the driving mechanism15 drives the probe card 4 such that a probe needle 5 abuts on the wafer1 based on a control signal S4 sent from the controller 11.Consequently, an electric stress is applied to the wafer 1 by the probecard 4.

[0121] According to the burn-in device 21 in accordance with thethirteenth embodiment, thus, the driving operation of the electricstress applying portion for applying the electric stress to the wafer 1is also controlled by the controller 11. Therefore, it is possible toenhance controllability as a system of the whole burn-in device.

[0122] Fourteenth Embodiment

[0123]FIG. 18 is a block diagram typically showing a part of a structureof a burn-in device according to a fourteenth embodiment of the presentinvention. For simplicity of the drawings, the temperature sensor 13shown in FIG. 16 is omitted. A burn-in device 22 comprises a hightemperature chuck 2H and a low temperature member 3L in the same manneras that in the ninth embodiment. In the fourteenth embodiment, the lowtemperature member 3L is fixed. Moreover, the burn-in device 22comprises a driving mechanism 17 for driving the high temperature chuck2H in vertical and transverse directions. Furthermore, the burn-indevice 22 comprises an electric stress applying portion having a probecard 4 fixed thereto. The driving mechanism 17 and the probe card 4 areconnected to a controller 11.

[0124] When a low temperature stress is to be applied to a wafer 1 atthe Step SP21 in the burn-in method according to the eighth embodiment,the driving mechanism 17 drives the high temperature chuck 2H toapproach to the low temperature member 3L based on a control signal S2sent from the controller 11. Consequently, the high temperature chuck 2Hand the low temperature member 3L approach to each other so that the lowtemperature stress is applied to the wafer 1.

[0125] When a high temperature stress and an electric stress are to beapplied to the wafer 1 at the Step SP22 in the burn-in method accordingto the eighth embodiment, the driving mechanism 17 drives the hightemperature chuck 2H such that the wafer 1 abuts on a probe needle 5based on the control signal S2 sent from the controller 11.Consequently, the high temperature stress is applied to the wafer 1 bythe high temperature chuck 2H and the electric stress is applied to thewafer 1 by the probe card 4 based on a control signal S4 sent from thecontroller 11.

[0126] While the description has been given to the example in which theburn-in device 22 according to the fourteenth embodiment is constitutedbased on the burn-in device according to the ninth embodiment, theburn-in device 22 according to the fourteenth embodiment can also beconstituted based on the burn-in devices according to the tenth andeleventh embodiments.

[0127] According to the burn-in device 22 in accordance with thefourteenth embodiment, thus, the application of the low temperaturestress through the low temperature member 3L, the application of thehigh temperature stress through the high temperature chuck 2H and theapplication of the electric stress through the probe card 4 arecontrolled by the controller 11. Therefore, it is possible to enhancecontrollability as a system of the whole burn-in device.

[0128] While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

What is claimed is:
 1. A burn-in method comprising the steps of: (a)applying one of a high temperature stress and a low temperature stressto an evaluation object; (b) applying an electric stress and the otherof said high temperature stress and said low temperature stress to saidevaluation object; and (c) deciding whether a failure is generated onsaid evaluation object or not after said steps (a) and (b).
 2. Theburn-in method according to claim 1, wherein said steps (a) and (b) areexecuted repetitively.
 3. The burn-in method according to claim 1,further comprising the step of (d) executing repair to a portion where afailure is generated in said evaluation object after said step (c).
 4. Aburn-in device comprising: one of a high temperature generating portionand a low temperature generating portion which has mounting surfacewhere an evaluation object is to be mounted; the other of said hightemperature generating portion and said low temperature generatingportion which is provided opposite to said mounting surface of said oneof said high temperature generating portion and said low temperaturegenerating portion and can be moved relatively to said one of said hightemperature generating portion and said low temperature generatingportion; an electric stress applying portion for applying an electricstress to said evaluation object; and an evaluating portion for decidingwhether a failure is generated on said evaluation object or not.
 5. Theburn-in device according to claim 4, wherein said other of said hightemperature generating portion and said low temperature generatingportion is provided with a plurality of through holes penetrating fromone main surface opposed to said mounting surface to the other mainsurface.
 6. The burn-in device according to claim 4, wherein said otherof said high temperature generating portion and said low temperaturegenerating portion partially applies a temperature stress to saidevaluation object.
 7. The burn-in device according to claim 4, furthercomprising a driving mechanism for driving at least one of said hightemperature generating portion and said low temperature generatingportion; and a control portion for controlling said driving mechanism.8. The burn-in device according to claim 7, further comprising atemperature sensor connected to said control portion and provided closeto said evaluation object.
 9. The burn-in device according to claim 7,wherein said electric stress applying portion is connected to saidcontrol portion.